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Architecture of parallel management kernel for PIE64

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PARLE '92 Parallel Architectures and Languages Europe (PARLE 1992)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 605))

Abstract

This paper describes the architecture of the parallel management kernel for the parallel inference engine PIE64, focusing on how to treat load distribution and scheduling in highly parallel symbolic processing. The kernel manages automatic load distribution and scheduling. The remaining task for a programmer is to employ parallel algorithms with sufficient concurrency. A programmer need not be concerned with load distribution, load partitioning, load assignment, parallelism explosion, exhaustion of resources, or execution efficiency. The paper also describes an evaluation of the load distribution method.

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References

  1. Arvind and Iannucci, R.A.: Two Fundamental Issues in Multiprocessing, Computation Structures Group Memo 226-6, Laboratory for Computer Science, MIT, (1987).

    Google Scholar 

  2. Casavant, T.L. and Kuhl, J.G.: A Taxonomy of Scheduling in General-Purpose Distributed Computing Systems, IEEE Trans. Software Eng., Vol.14, No.2, pp.141–154 (1988).

    Article  Google Scholar 

  3. Shapiro, E.: Systolic Programming: A Paradigm of Parallel Processing, Proc. of the Int. Conf. on Fifth Generation Computer Systems, pp.458–470 (1984).

    Google Scholar 

  4. Takeda, Y., Nakashima, H., Masuda, K., Chikayama, T. and Taki, K.: A Load Balancing Mechanism for Large Scale Multiprocessor Systems and Its Implementation, Proc. of the Int. Conf. on Fifth Generation Computer Systems, pp.978–986 (1988).

    Google Scholar 

  5. Ueda, K.: Guarded Horn Clauses, ICOT Technical Report TR-003, Institute for New Generation Computer Technology, Tokyo (1985).

    Google Scholar 

  6. Nilsson, M. and Tanaka, H.: Massively Parallel Implementation of Flat GHC on the Connection Machine, Proc. of the Int. Conf. on Fifth Generation Computer Systems, pp.1031–1040 (1988).

    Google Scholar 

  7. The Fourth Research Laboratory at ICOT: KL1 Programming introductory course / beginner's course / middle course (in Japanese), Institute for New Generation Computer Technology, Tokyo, p.177 (1989).

    Google Scholar 

  8. Hidaka, Y., Koike, H., Tatemura, J. and Tanaka, H.: A Static Load Partitioning Method Based on Execution Profile for Committed Choice Languages, Proc. of the 1991 Int. Symp. on Logic Programming, pp.470–484 (1991).

    Google Scholar 

  9. Koike, H. and Tanaka, H.: Generation Scavenging GC on Distributed-Memory Parallel Computers, Proc. of High Performance and Parallel Lisp Workshop, London, (1990).

    Google Scholar 

  10. Koike, H. and Tanaka, H.: Parallel Inference Engine PIE64 (in Japanese), bit extra number — Parallel Computer Architecture, Vol.21, No.4, pp.488–497 (1989).

    Google Scholar 

  11. Takahashi, E., Koike, H. and Tanaka, H.: A Study of a High Bandwidth and Low Latency Interconnection Network in PIE64, Proc. of IEEE Pacific Rim Conf. on Communications, Computers and Signal Processing, pp.5–8 (1991).

    Google Scholar 

  12. Hidaka, Y., Koike, H. and Tanaka, H.: The Architecture of the Inference Unit of Parallel Inference Engine PIE64 (in Japanese), IEICE Technical Report CPSY90-44, The Institute of Electronics, Information and Communication Engineers, Japan, pp.37–42 (1990).

    Google Scholar 

  13. Shimada, K., Koike, H. and Tanaka, H.: The Inference Processor UNIRED II: Evaluation by Simulation (in Japanese), Proc. of Joint Symp. on Parallel Processing '91, Info. Processing Society of Japan, pp.85–92 (1991).

    Google Scholar 

  14. Shimizu, T., Koike, H. and Tanaka, H.: Details of the Network Interface Processor for PIE64 (in Japanese), SIG Reports on Computer Architecture, Info. Processing Society of Japan, 87–5 (1991).

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Electrical Engineering, The University of Tokyo, 7-3-1, Hongo, Bunkyo-ku, 113, Tokyo, Japan

    Yasuo Hidaka, Hanpei Koike & Hidehiko Tanaka

Authors
  1. Yasuo Hidaka
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  2. Hanpei Koike
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  3. Hidehiko Tanaka
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Editor information

Daniel Etiemble Jean-Claude Syre

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© 1992 Springer-Verlag Berlin Heidelberg

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Hidaka, Y., Koike, H., Tanaka, H. (1992). Architecture of parallel management kernel for PIE64. In: Etiemble, D., Syre, JC. (eds) PARLE '92 Parallel Architectures and Languages Europe. PARLE 1992. Lecture Notes in Computer Science, vol 605. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-55599-4_118

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  • DOI: https://doi.org/10.1007/3-540-55599-4_118

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-55599-5

  • Online ISBN: 978-3-540-47250-6

  • eBook Packages: Springer Book Archive

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