Abstract
A new carry-free division algorithm will be described; it is based on the properties of RSD arithmetic to avoid carry propagation and uses the minimum hardware per bit i.e. one full-adder. Its application to a 1024 bits RSA cryptographic chip will be presented. Thanks to the features of this new algorithm, high performance (8 kbits/s for 1024 bits words) was obtained for relatively small area and power consumption (80 mm2 in a 2 μm CMOS process and 500 mW at 25 MHz).
This work has been supported by the Région Wallonne of Belgium and by the FNRS (National Fund for Scientific Research).
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Vandemeulebroecke, A., Vanzieleghem, E., Denayer, T., Jespers, P.G.A. (1990). A Single Chip 1024 Bits RSA Processor. In: Quisquater, JJ., Vandewalle, J. (eds) Advances in Cryptology — EUROCRYPT ’89. EUROCRYPT 1989. Lecture Notes in Computer Science, vol 434. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46885-4_24
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