Abstract
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to establish right comparisons between different implementations of gate- clocked counters is presented. Basically two ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits. The right selection of bits where clock gating must be applied and the suited composition of groups of bits is essential when applying this technique. We have found groupment of bits is the best option when applying clock gating to reduce power consumption and specially to reduce noise generation.
This work has been sponsored by the Spanish MCYT TIC2000-1350 MODEL and TIC2001- 2283 VERDI Projects
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Parra, P., Acosta, A., Valencia, M. (2002). Selective Clock-Gating for Low Power/Low Noise Synchronous Counters. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_45
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DOI: https://doi.org/10.1007/3-540-45716-X_45
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