VLSI Implementation of a Low-Power High-Speed Self-Timed Adder

Abstract

Usually, self-timed modules for asynchronous system design are realized by means of dynamic logic circuits. Moreover, in order to easily detect the end-completion, dual-rail encoding is preferred. Therefore, dynamic differential logic circuits (such as Differential Cascode Voltage Switch Logic (DCVSL)) are widely used because they intrinsically produce both true and inverted values of the output. However, the use of dynamic logic circuits presents two main difficulties: i) design and testing is more complex, ii) often it is not possible to use standard design methodology. This paper presents a new static logic VLSI implementation of a high-speed self-timed adder based on the statistical carry look-ahead addition technique. A 56-bit adder designed in this way has been realized using 0.6μm AMS Standard Cells. It requires about 0.6mm² silicon area, has an average addition of about 4 ns, and dissipates only 20.5 mW in the worst case.