Skip to main content
SpringerLink
Log in

The Impact of Cache Coherence Protocols on Parallel Logic Programming Systems

  • Conference paper
  • First Online:
Computational Logic — CL 2000 (CL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNAI,volume 1861))

Included in the following conference series:

  • 594 Accesses

Abstract

In this paper we use execution-driven simulation of a scalable multiprocessor to evaluate the performance of the Andorra-I parallel logic programming system under invalidate and update-based protocols. We use two versions of Andorra-I. One of them was originally designed for bus-based multiprocessors, while the other is optimised for scalable architectures. We study a well-known invalidate protocol and two different update-based protocols. Our results show that for our sample logic programs the update-based protocols outperform their invalidate-based counterpart for the original version of Andorra-I. In contrast, the optimised version of Andorra-I benefits the most from the invalidate-based protocol, but a hybrid update-based protocol performs as well as the invalidate protocol in most cases. We conclude that parallel logic programming systems can consistently benefit from hybrid update-based protocols.

This work was sponsored by CNPq, Brazilian Research Council.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Khayri A. M. Ali and Roland Karlsson. The Muse Or-parallel Prolog Model and its Performance. In Proceedings of the 1990 North American Conference on Logic Programming, pages 757–776. MIT Press, October 1990.

    Google Scholar 

  2. Reem Bahgat. Solving Resource Allocation Problems in Pandora. Technical report, Imperial College, Department of Computing, 1990.

    Google Scholar 

  3. Anthony Beaumont, S. Muthu Raman, and Péter Szeredi. Flexible Scheduling of Or-Parallelism in Aurora: The Bristol Scheduler. In Aarts, E. H. L. and van Leeuwen, J. and Rem, M., editor, PARLE91: Conference on Parallel Architectures and Languages Europe, volume 2, pages 403–420. Springer Verlag, June 1991. Lecture Notes in Computer Science 506.

    Google Scholar 

  4. Johan Bevemyr, Thomas Lindgren, and Häkan Millroth. Reform Prolog: The Language and its Implementation. In Proceedings of the Tenth International Conference on Logic Programming, pages 283–298. MIT Press, June 1993.

    Google Scholar 

  5. R. Bianchini and L. I. Kontothanassis. Algorithms for Categorizing Multiprocessor Communication Under Invalidate and Update-Based Coherence Protocols. In Proceedings of the 28th Annual Simulation Symposium, April 1995.

    Google Scholar 

  6. J. A. Crammond. Implementation of Committed Choice Logic Languages on Shared Memory Multiprocessors. PhD thesis, Heriot-Watt University, Edinburgh, May 1988. Research Report PAR 88/4, Dept. of Computing, Imperial College, London.

    Google Scholar 

  7. J. A. Crammond. The Abstract Machine and Implementation of Parallel Parlog. Technical report, Dept. of Computing, Imperial College, London, June 1990.

    Google Scholar 

  8. I. C. Dutra. Distributing And-and Or-Work in the Andorra-I Parallel Logic Programming System. PhD thesis, University of Bristol, Department of Computer Science, February 1995. available at http://www.cos.ufrj.br/~ines.

  9. James R. Goodman. Using Cache Memory to Reduce Processor-Memory Traffic. In Proceedings of the 10th International Symposium on Computer Architecture, pages 124–131, 1983.

    Google Scholar 

  10. Gopal Gupta, M. V. Hermenegildo, E. Pontelli, and V. Santos Costa. ACE: And/Or-parallel Copying-based Execution of Logic Programs. In Proceedings of the Eleventh International Conference on Logic Programming, Italy, June 1994.

    Google Scholar 

  11. Gopal Gupta, Enrico Pontelli, and Manuel Hermenegildo. &ACE: A High Performance Parallel Prolog System. In Proceedings of the First International Symposium on Parallel Symbolic Computation, PASCO’94, 1994.

    Google Scholar 

  12. M. V. Hermenegildo and K. Greene. &-Prolog and its Performance: Exploiting Independent And-Parallelism. In Proceedings of the Seventh International Conference on Logic Programming, pages 253–268. MIT Press, June 1990.

    Google Scholar 

  13. Markus Hitz and Erich Kaltofen, editors. Proceedings of the Second International Symposium on Parallel Symbolic Computation, PASCO’97, July 1997.

    Google Scholar 

  14. A. R. Karlin, M. S. Manasse, L. Rudolph, and D. D. Sleator. Competitive snoopy caching. Algorithmica, 3:79–119, 1988.

    Article  MATH  MathSciNet  Google Scholar 

  15. L. Kovács. An Incremental Prolog System development for the Floor Plan Design by Dissecting. In Proceedings of the International Conference on Practical Application of Prolog, volume 2, 1992.

    Google Scholar 

  16. D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy. The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor. Proceedings of the 17th ISCA, pages 148–159, May 1990.

    Google Scholar 

  17. Ewing Lusk, David H. D. Warren, Seif Haridi, et al. The Aurora Or-parallel Prolog System. New Generation Computing, 7(2, 3):243–271, 1990.

    Article  Google Scholar 

  18. E. M. McCreight. The Dragon Computer System, an Early Overview. In NATO Advanced Study Institute on Microarchitecture of VLSI Computers, July 1984.

    Google Scholar 

  19. Johan Montelius. Penny, A Parallel Implementation of AKL. In ILPS’94 Post-Conference Workshop in Design and Implementation of Parallel Logic Programming Systems, Ithaca, NY, USA, November 1994.

    Google Scholar 

  20. S. Raina, D. H. D. Warren, and J. Cownie. Parallel Prolog on a Scalable Multiprocessor. In Peter Kacsuk and Michael J. Wise, editors, Implementations of Distributed Prolog, pages 27–44. Wiley, 1992.

    Google Scholar 

  21. V. Santos Costa and R. Bianchini. Optimising Parallel Logic Programming Systems for Scalable Machines. In Proceedings of the EUROPAR’98, pages 831–841, Sep 1998.

    Google Scholar 

  22. V. Santos Costa, R. Bianchini, and I. C. Dutra. Evaluating the Impact of Coherence Protocols on Parallel Logic Programming Systems. In Proceedings of the 5th EUROMICRO Workshop on Parallel and Distributed Processing, pages 376–381, 1997. Also available as technical report ES-389/96, COPPE/Systems Engineering, May, 1996.

    Google Scholar 

  23. V. Santos Costa, R. Bianchini, and I. C. Dutra. Parallel Logic Programming Systems on Scalable Multiprocessors. In Proceedings of the 2nd International Symposium on Parallel Symbolic Computation, PASCO’97 Erich Kaltofen, editors [13], pages 58–67, July 1997.

    Google Scholar 

  24. V. Santos Costa, D. H. D. Warren, and R. Yang. Andorra-I: A Parallel Prolog System that Transparently Exploits both And-and Or-Parallelism. In Third ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming, pages 83–93. ACM press, April 1991. SIGPLAN Notices vol 26(7), July 1991.

    Google Scholar 

  25. Kish Shen. Studies of And/Or Parallelism in Prolog. PhD thesis, Computer Laboratory, University of Cambridge, 1992.

    Google Scholar 

  26. T. Chikayama, T. Fujise, and H. Yashiro. A Portable and Reasonably Efficient Implementation of KL1. In Proceedings of the Eleventh International Conference on Logic Programming, June 1993.

    Google Scholar 

  27. Charles P. Thacker, David G. Conroy, and Lawrence C. Stewart. The alpha demonstration unit: A high-performance multiprocessor for software and chip development. Digital Technical Journal, 4(4):51–65, 1992.

    Google Scholar 

  28. Evan Tick. Memory Performance of Prolog Architectures. Kluwer Academic Publishers, Norwell, MA 02061, 1987.

    Google Scholar 

  29. J. E. Veenstra and R. J. Fowler. MINT: A Front End for Efficient Simulation of Shared-Memory Multiprocessors. In Proceedings of the 2nd International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems (MASCOTS’ 94), 1994.

    Google Scholar 

  30. David H. D. Warren. The Andorra model. Presented at Gigalips Project workshop, University of Manchester, March 1988.

    Google Scholar 

  31. David H. D. Warren and Fernando C. N. Pereira. An Efficient Easily Adaptable System for Interpreting Natural Language Queries. Technical Note, Dept of AI, University of Edinburgh, 1981.

    Google Scholar 

  32. Rong Yang, Tony Beaumont, Inês Dutra, Vítor Santos Costa, and David H. D. Warren. Performance of the Compiler-Based Andorra-I System. In Proceedings of the Tenth International Conference on Logic Programming, pages 150–166. MIT Press, June 1993.

    Google Scholar 

  33. Rong Yang, Vítor Santos Costa, and David H. D. Warren. The Andorra-I Engine: A parallel implementation of the Basic Andorra model. In Proceedings of the Eighth International Conference on Logic Programming, pages 825–839. MIT Press, 1991.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. COPPE Systems Engineering, Federal University of Rio de Janeiro, Rio de Janeiro, Brazil, 21945-970

    Inês de Castro Dutra, Vítor Santos Costa & Ricardo Bianchini

  2. Department of Computer Science, Rutgers University, Piscataway, NJ, 08854-8019

    Ricardo Bianchini

Authors
  1. Inês de Castro Dutra
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Vítor Santos Costa
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Ricardo Bianchini
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. The Australian National University, Australia

    John Lloyd

  2. Simon Fraser University, Canada

    Veronica Dahl

  3. Universität Koblenz, Germany

    Ulrich Furbach

  4. The University of Birmingham, UK

    Manfred Kerber

  5. University of Manchester, UK

    Kung-Kiu Lau

  6. The Pennsylvania State University, USA

    Catuscia Palamidessi

  7. Universidade Nova de Lisboa, Portugal

    Luís Moniz Pereira

  8. The Hebrew University of Jerusalem, Israel

    Yehoshua Sagiv

  9. The University of Melbourne, Australia

    Peter J. Stuckey

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

de Castro Dutra, I., Costa, V.S., Bianchini, R. (2000). The Impact of Cache Coherence Protocols on Parallel Logic Programming Systems. In: Lloyd, J., et al. Computational Logic — CL 2000. CL 2000. Lecture Notes in Computer Science(), vol 1861. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44957-4_86

Download citation

  • DOI: https://doi.org/10.1007/3-540-44957-4_86

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67797-0

  • Online ISBN: 978-3-540-44957-7

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation