Abstract
In this paper, a high performance asynchronous on-chip bus designed in a Globally Asynchronous Locally Synchronous (GALS) style is proposed. The asynchronous on-chip bus is capable of handling multiple outstanding transactions and in-order completion to achieve a high performance, which is implemented with distributed and modularized control unit in a layered interface. The architecture of asynchronous on-chip bus is discussed and implemented for simulations. Simulation results show that throughput of the proposed asynchronous on-chip bus with multiple outstanding transactions and in-order transaction completion is increased by 31.3%, while power consumption overhead is only 6.76%, as compared to an asynchronous on-chip bus with a single outstanding transaction.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Bainbridge, W.J.: Asynchronous System-on-Chip Interconnect. PhD thesis, Univ. of Manchester, UK (2000)
Jung, E.G., Choi, B.S., Lee, D.I.: High performance asynchronous bus for SoC. In: Proceedings of IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, vol. 5, pp. 505–508 (2003)
Salminen, E., Lahtinen, V., Kuusilinna, K., Hamalainen, T.: Overview of bus-based system-on-chip interconnections. In: Proceedings of IEEE International Symposium on Circuits and Systems, Phoenix-Scottsdale, AZ, vol. 2, pp. 372–275 (2002)
ARM: AMBA AXI Protocol Specification (2003)
Kim, E., Lee, J.G., Lee, D.I.: Automatic process-oriented control control generation for asynchronous high-level synthesis. In: Proceedings of IEEE International Symposium on Asynchronous Circuits and Systems, Eilat, Israel, pp. 104–105 (2000)
Zimmermann, H.: OSI reference model–the ISO model of architecture for open systems interconnection. IEEE Transactions on Communications 28, 425–432 (1980)
Cortadella, J., Kishinevsky, M., Kondratyev, A., Lavagno, L., Yakovlev, A.: Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers. IEICE Transactions on Information and Systems E-80D, 315–325 (1997)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Jung, EG., Hong, EP., Jhang, KS., Lee, JA., Har, DS. (2005). Self-timed Interconnect with Layered Interface Based on Distributed and Modularized Control for Multimedia SoCs. In: Ho, YS., Kim, H.J. (eds) Advances in Multimedia Information Processing - PCM 2005. PCM 2005. Lecture Notes in Computer Science, vol 3767. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11581772_44
Download citation
DOI: https://doi.org/10.1007/11581772_44
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30027-4
Online ISBN: 978-3-540-32130-9
eBook Packages: Computer ScienceComputer Science (R0)