Regular ArticleArchitectural Improvements for a Data-Driven VLSI Processing Array
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Advances in the dataflow computational model
1999, Parallel ComputingImproved schemes for mapping arbitrary algorithms onto processor meshes
1996, Parallel ComputingThe architecture of a highly reconfigurable RISC dataflow array processor
1997, International Journal of ElectronicsEfficient run-time program allocation on a parallel coprocessor
1995, Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)Fault-tolerant mapping onto VLSI/WSI processor arrays
1994, Conference Proceedings of the EUROMICRO
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